This present invention relates to a fabrication method for forming a gate structure through an amorphous silicon layer and applications thereof, and more particularly to a fabrication method that uses a same manufacturing process and a same in situ chamber to form an amorphous silicon layer and the applications thereof.
Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is an important basic electronic element in the VLSI technology. It is formed by stacking a metal layer, an oxide layer and a semiconductor layer that have different thicknesses together from up and down in this order. In the conventional fabrication process, silicon is the primary source of the semiconductor layer. The oxide layer mainly is silicon dioxide. The metal layer is made from polysilicon which is characteristically similar to the silicon substrate to be in contact with the oxide layer.
In the conventional techniques, the polysilicon is formed through low pressure chemical vapor deposition (LPCVD) by heating and decomposing silane (i.e., SiH4). The reaction formula is as follow:SiH4(g)→Si(s)+2H2(g)When the temperature rises to 575° C. to 650° C., the deposited silicon mostly exists in the form of polysilicon. Hence in the practical application for forming the polysilicon, the reaction temperature usually is controlled between 600° C. and 650° C., and the pressure between 0.3 to 0.6 Torr.
After the polysilicon has been formed, in order to reduce the resistance and increase the conductivity, a dope process is applied to the polysilicon by adding a small amount of dopant to transform the polysilicon to an electric conductor.
The resulting structure previously discussed includes a silicon substrate 2, a silicon dioxide film 3 and a doped polysilicon layer 4 to become a planar MOSFET element 1 (referring to FIG. 1).
FIG. 2 shows the structure of a trench MOSFET element 10. It has a vertical gate channel different from the horizontal structure of the planar MOSFET mentioned above. There is a trench 12 filled with polysilicon 14 which is isolated from a silicon area 16 by an insulation film 18. There is a main layer 20 formed in an epitaxial layer 22 by diffusion. A doped area 24 also is formed in the main layer 20 by diffusion. The polysilicon 14 and the insulation film 18 in the trench 12 form respectively a gate structure 26 and a gate dielectric layer 28.
The planar MOSFET element shown in FIG. 1 is used as an example to explain the problems that have occurred in the conventional technique. In general, when the element 1 is undergoing the sequential thermal process, the doped ions (such as boron, arsenic, or phosphorus) easily penetrate the silicon dioxide layer 3 into the silicon substrate 2. This will result in shift of electric characteristics of the MOSFET 1 (such as the threshold voltage, and current of the drain and source) and ineffectiveness of the element.
Moreover, in the conventional fabrication process, in order to prevent the dopant ions in the polysilicon layer 4 from penetrating the silicon dioxide film 3 into the silicon substrate 2, an extra un-doped polysilicon layer 5 is formed between the doped polysilicon layer and the silicon dioxide film 3 (referring to FIG. 3). But even with the un-doped polysilicon layer 5, the dopant still tends to penetrate the silicon dioxide film 3 and the un-doped polysilicon layer 5 through the grain boundary of the doped polysilicon layer 4, and the boundary of the silicon dioxide film 3 and the silicon substrate 2.